TID Results of 22-nm FDSOI SRAM Published in IEEE TNS
IEEE Transactions on Nuclear Science (TNS) is a peer-reviewed journal with a longstanding history of excellence and notable contributions to the radiation effects community. Alphacore is excited to be recognized for its achievements in total-dose testing on fully-depleted silicon-on-insulator (FDSOI) static random access memory (SRAM) with its latest publication in the August 2023 issue of TNS. Tests were conducted at multiple voltages, with and without read/write assists in SRAM. The results demonstrate cell stability past 200 krad(Si) TID in standard operational modes. The impact of read and write assists and read timing are examined, along with input-output (IO)-level translation circuit failures and anomalous circuit failures attributable to IO at relatively low TID, impact of voltage bias, and post-irradiation annealing behavior.
Fully-Depleted Silicon-on-Insulator (FDSOI) Static Random Access Memory (SRAM):
Due to harsh radiation conditions in space, aerospace applications require a strong tolerance to radiation effects. Static random access memory (SRAM) is commonly used in ground- and space-based application specific integrated circuits (ASICs), meaning it must have some inherent radiation tolerance or that mitigation techniques must be implemented. Fully-depleted silicon-on-insulator (FDSOI) processes have recently been introduced that are relatively low-cost while also allowing to compensate the environment-caused threshold voltage (Vth) shift. FDSOI processes have high single event effect (SEE) immunity; however, TID-induced Vth shifts are worse than modern bulk and FinFET processes due to the buried oxide (BOX) that retains positive charge, decreasing pMOS transistor current drive and increasing nMOS current drive and leakage. The article published in TNS presents TID results on 2-Mbit compiled SRAMs processed in GlobalFoundries’ 22-nm FDSOI (22FDX) process. The tests were run with a variety of test patterns to identify specific failure points.
In the test, standard SRAM circuits are used. Read and write assist circuits are also used, and the column outputs are fully differential via read and write paths. The post-radiation Vth shift, resulting in column leakage, was hypothesized to be a significant failure mode due to one cell in a column in the opposite state. The test was specifically designed with a pattern to pinpoint this failure mode by varying the test patterns as well as the bias to determine whether the destabilization is more affected by reads and writes that matched or differed from the irradiation state.
The circuits were initially tested to a dose of 270 krad, resulting in early one-to-zero failures in certain patterns with all patterns failing with the same mechanism at 230 krad. The next device under test (DUT) was irradiated to over 1.3 Mrad. Similar failure mechanisms were observed, with the first one-to-zero full words failures at 110 krad and full failure by 350 krad. All testing was performed while the die was being irradiated; tests were repeated post-irradiation. While the connections were the same, the results were the same; however, when the ribbon cables were removed and the FPGA board was connected directly to the DUT board, the all-one failures disappeared, leading to the conclusion that those specific failure patterns were related to IO circuits in the test chips rather than the SRAM itself. The impact of the supply voltage was examined, showing a distinct impact of bias voltage on fail count, especially in the lower dose range. Post-irradiation anneal behavior was monitored for three months, quantifying the number of failing cells in each direction versus time.
Experiment setup for robust TID cell stability testing
Ultimately, it was concluded that the TID-induced shift in Vth is due mainly to positive charge deposited in the buried oxide, strengthening nMOS but weakening pMOS. The problem with using SRAM at low voltage is due to the large number of storage cells in SRAM and their sensitivity to random variations. The early systematic failures were attributed to TID, ribbon cable loading, and level shifter circuit marginalities, whereas the experimental TID results show that the 6-T SRAM cells are robust up to doses around 200 krad(Si) even at reduced operating voltage. The variety of test patterns illuminated specific failure modes and shed light on usage and environment conditions for desired robustness applications.
Read the complete IEEE article here
